[ DevCourseWeb.com ] Udemy - Verilog HDL programming with practical approach

File Name

Size

Get Bonus Downloads Here.url

182 B

~Get Your Files Here !/01 - Introduction to the course/001 Preview.mp4

85 MB

~Get Your Files Here !/01 - Introduction to the course/001 Preview_en.vtt

15 kB

~Get Your Files Here !/01 - Introduction to the course/002 Sample program on edaplayground.mp4

88 MB

~Get Your Files Here !/01 - Introduction to the course/002 Sample program on edaplayground_en.vtt

13 kB

~Get Your Files Here !/02 - Introduction to Verilog HDL/001 Verilog fundamentals.mp4

166 MB

~Get Your Files Here !/02 - Introduction to Verilog HDL/001 Verilog fundamentals_en.vtt

30 kB

~Get Your Files Here !/03 - VLSI design flow ( FPGA & ASIC)/001 VLSI Design flow (FPGA & ASIC).mp4

76 MB

~Get Your Files Here !/03 - VLSI design flow ( FPGA & ASIC)/001 VLSI Design flow (FPGA & ASIC)_en.vtt

14 kB

~Get Your Files Here !/03 - VLSI design flow ( FPGA & ASIC)/002 FPGA vs ASIC.mp4

80 MB

~Get Your Files Here !/03 - VLSI design flow ( FPGA & ASIC)/002 FPGA vs ASIC_en.vtt

8.7 kB

~Get Your Files Here !/04 - Three levels of verilog design Description/001 Three levels of verilog design Description.mp4

33 MB

~Get Your Files Here !/04 - Three levels of verilog design Description/001 Three levels of verilog design Description_en.vtt

3.7 kB

~Get Your Files Here !/04 - Three levels of verilog design Description/002 Example mux_2x1 with 3 abstracts models.mp4

9.1 MB

~Get Your Files Here !/04 - Three levels of verilog design Description/002 Example mux_2x1 with 3 abstracts models_en.vtt

1.8 kB

~Get Your Files Here !/05 - Verilog Language constructs, Data types & Compiler Directives/001 Language constructs -Comments, keywords, identifier, Number specific, Operators.mp4

14 MB

~Get Your Files Here !/05 - Verilog Language constructs, Data types & Compiler Directives/001 Language constructs -Comments, keywords, identifier, Number specific, Operators_en.vtt

2.2 kB

~Get Your Files Here !/05 - Verilog Language constructs, Data types & Compiler Directives/002 Datatypes - net,reg, integer, real, string, time, Parameter, Vector,Array,Memory.mp4

18 MB

~Get Your Files Here !/05 - Verilog Language constructs, Data types & Compiler Directives/002 Datatypes - net,reg, integer, real, string, time, Parameter, Vector,Array,Memory_en.vtt

3.0 kB

~Get Your Files Here !/05 - Verilog Language constructs, Data types & Compiler Directives/003 Compiler Directives.mp4

16 MB

~Get Your Files Here !/05 - Verilog Language constructs, Data types & Compiler Directives/003 Compiler Directives_en.vtt

2.0 kB

~Get Your Files Here !/06 - Verilog Program structure/001 Verilog Program Structure -Module.mp4

7.4 MB

~Get Your Files Here !/06 - Verilog Program structure/001 Verilog Program Structure -Module_en.vtt

1.1 kB

~Get Your Files Here !/06 - Verilog Program structure/002 Ports.mp4

11 MB

~Get Your Files Here !/06 - Verilog Program structure/002 Ports_en.vtt

1.8 kB

~Get Your Files Here !/06 - Verilog Program structure/003 Port Connection Rules.mp4

13 MB

~Get Your Files Here !/06 - Verilog Program structure/003 Port Connection Rules_en.vtt

1.9 kB

~Get Your Files Here !/06 - Verilog Program structure/004 Design Methodologies Approaches.mp4

4.7 MB

~Get Your Files Here !/06 - Verilog Program structure/004 Design Methodologies Approaches_en.vtt

849 B

~Get Your Files Here !/07 - Gate level modeling/001 Gate Level Model Introduction.mp4

3.4 MB

~Get Your Files Here !/07 - Gate level modeling/001 Gate Level Model Introduction_en.vtt

655 B

~Get Your Files Here !/07 - Gate level modeling/002 Example 4x1 Mux.mp4

5.4 MB

~Get Your Files Here !/07 - Gate level modeling/002 Example 4x1 Mux_en.vtt

932 B

~Get Your Files Here !/07 - Gate level modeling/003 Example Full Adder.mp4

3.6 MB

~Get Your Files Here !/07 - Gate level modeling/003 Example Full Adder_en.vtt

733 B

~Get Your Files Here !/07 - Gate level modeling/004 Tri-state Buffers with Examples.mp4

13 MB

~Get Your Files Here !/07 - Gate level modeling/004 Tri-state Buffers with Examples_en.vtt

2.0 kB

~Get Your Files Here !/07 - Gate level modeling/005 Array of Instance with example.mp4

11 MB

~Get Your Files Here !/07 - Gate level modeling/005 Array of Instance with example_en.vtt

1.6 kB

~Get Your Files Here !/08 - Data flow modeling/001 Data flow Modeling assign statement.mp4

13 MB

~Get Your Files Here !/08 - Data flow modeling/001 Data flow Modeling assign statement_en.vtt

2.3 kB

~Get Your Files Here !/08 - Data flow modeling/002 Operators.mp4

17 MB

~Get Your Files Here !/08 - Data flow modeling/002 Operators_en.vtt

1.9 kB

~Get Your Files Here !/08 - Data flow modeling/003 Arithmetic Operators.mp4

8.5 MB

~Get Your Files Here !/08 - Data flow modeling/003 Arithmetic Operators_en.vtt

1.4 kB

~Get Your Files Here !/08 - Data flow modeling/004 Logical Operators.mp4

13 MB

~Get Your Files Here !/08 - Data flow modeling/004 Logical Operators_en.vtt

1.6 kB

~Get Your Files Here !/08 - Data flow modeling/005 Example Full Adder Logical operators.mp4

3.8 MB

~Get Your Files Here !/08 - Data flow modeling/005 Example Full Adder Logical operators_en.vtt

811 B

~Get Your Files Here !/08 - Data flow modeling/006 Example Full Adder Arithmetic operators.mp4

2.8 MB

~Get Your Files Here !/08 - Data flow modeling/006 Example Full Adder Arithmetic operators_en.vtt

776 B

~Get Your Files Here !/08 - Data flow modeling/007 Example Binary to Gray code converter.mp4

4.6 MB

~Get Your Files Here !/08 - Data flow modeling/007 Example Binary to Gray code converter_en.vtt

891 B

~Get Your Files Here !/08 - Data flow modeling/008 Logical and , Logical or (&&, ).mp4

5.6 MB

~Get Your Files Here !/08 - Data flow modeling/008 Logical and , Logical or (&&, )_en.vtt

1.4 kB

~Get Your Files Here !/08 - Data flow modeling/009 Shift operators Leftright Shift.mp4

18 MB

~Get Your Files Here !/08 - Data flow modeling/009 Shift operators Leftright Shift_en.vtt

2.3 kB

~Get Your Files Here !/08 - Data flow modeling/010 Shifting without shift operator , just with concatenation operator.mp4

4.3 MB

~Get Your Files Here !/08 - Data flow modeling/010 Shifting without shift operator , just with concatenation operator_en.vtt

1.3 kB

~Get Your Files Here !/08 - Data flow modeling/011 Ternary operator Example 2x1 MUX, 4x1 MUX.mp4

14 MB

~Get Your Files Here !/08 - Data flow modeling/011 Ternary operator Example 2x1 MUX, 4x1 MUX_en.vtt

3.2 kB

~Get Your Files Here !/08 - Data flow modeling/012 Relational operators Example Comparator.mp4

4.5 MB

~Get Your Files Here !/08 - Data flow modeling/012 Relational operators Example Comparator_en.vtt

854 B

~Get Your Files Here !/08 - Data flow modeling/013 Equality (==) , case Equality (===) operators.mp4

7.1 MB

~Get Your Files Here !/08 - Data flow modeling/013 Equality (==) , case Equality (===) operators_en.vtt

1.9 kB

~Get Your Files Here !/08 - Data flow modeling/014 Reduction operator Example Parity Generator.mp4

7.1 MB

~Get Your Files Here !/08 - Data flow modeling/014 Reduction operator Example Parity Generator_en.vtt

1.3 kB

~Get Your Files Here !/08 - Data flow modeling/38061230-arthm1.mp4

3.8 MB

~Get Your Files Here !/09 - Behavioral Modeling/001 Behavioral Modeling - Introduction.mp4

67 MB

~Get Your Files Here !/09 - Behavioral Modeling/001 Behavioral Modeling - Introduction_en.vtt

7.8 kB

~Get Your Files Here !/09 - Behavioral Modeling/002 Behavioral Modeling Constructs.mp4

15 MB

~Get Your Files Here !/09 - Behavioral Modeling/002 Behavioral Modeling Constructs_en.vtt

1.8 kB

~Get Your Files Here !/09 - Behavioral Modeling/003 Procedural Blocks- initial & always.mp4

61 MB

~Get Your Files Here !/09 - Behavioral Modeling/003 Procedural Blocks- initial & always_en.vtt

7.6 kB

~Get Your Files Here !/09 - Behavioral Modeling/004 Example Clock Generation.mp4

8.4 MB

~Get Your Files Here !/09 - Behavioral Modeling/004 Example Clock Generation_en.vtt

2.1 kB

~Get Your Files Here !/09 - Behavioral Modeling/005 Assignment Statements - Blocking & Non-blocking.mp4

63 MB

~Get Your Files Here !/09 - Behavioral Modeling/005 Assignment Statements - Blocking & Non-blocking_en.vtt

7.0 kB

~Get Your Files Here !/09 - Behavioral Modeling/006 Mechanism in Non-blocking.mp4

4.4 MB

~Get Your Files Here !/09 - Behavioral Modeling/006 Mechanism in Non-blocking_en.vtt

1.2 kB

~Get Your Files Here !/09 - Behavioral Modeling/007 Concurrency.mp4

6.4 MB

~Get Your Files Here !/09 - Behavioral Modeling/007 Concurrency_en.vtt

1.2 kB

~Get Your Files Here !/09 - Behavioral Modeling/008 Advantage of Non-blocking assignment Example swapping.mp4

10 MB

~Get Your Files Here !/09 - Behavioral Modeling/008 Advantage of Non-blocking assignment Example swapping_en.vtt

1.4 kB

~Get Your Files Here !/09 - Behavioral Modeling/009 Advantage of Non-blocking assignment Example Pipelining.mp4

38 MB

~Get Your Files Here !/09 - Behavioral Modeling/009 Advantage of Non-blocking assignment Example Pipelining_en.vtt

5.6 kB

~Get Your Files Here !/09 - Behavioral Modeling/010 if-else statement Example 4x1 Mux.mp4

30 MB

~Get Your Files Here !/09 - Behavioral Modeling/010 if-else statement Example 4x1 Mux_en.vtt

4.3 kB

~Get Your Files Here !/09 - Behavioral Modeling/011 Case – statement Example 4x1 Mux.mp4

34 MB

~Get Your Files Here !/09 - Behavioral Modeling/011 Case – statement Example 4x1 Mux_en.vtt

3.6 kB

~Get Your Files Here !/09 - Behavioral Modeling/012 Advantage of Case over if-else.mp4

8.0 MB

~Get Your Files Here !/09 - Behavioral Modeling/012 Advantage of Case over if-else_en.vtt

1.0 kB

~Get Your Files Here !/09 - Behavioral Modeling/013 Loops while, for, repeat, forever.mp4

7.2 MB

~Get Your Files Here !/09 - Behavioral Modeling/013 Loops while, for, repeat, forever_en.vtt

1.4 kB

~Get Your Files Here !/09 - Behavioral Modeling/014 Parallel blocks - fork-join.mp4

11 MB

~Get Your Files Here !/09 - Behavioral Modeling/014 Parallel blocks - fork-join_en.vtt

1.7 kB

~Get Your Files Here !/09 - Behavioral Modeling/015 Combinational Logic Circuit Examples 8x1 Mux.mp4

7.6 MB

~Get Your Files Here !/09 - Behavioral Modeling/015 Combinational Logic Circuit Examples 8x1 Mux_en.vtt

1.8 kB

~Get Your Files Here !/09 - Behavioral Modeling/016 Example 8x1 Mux using 4x1 mux and 2x1 mux.mp4

17 MB

~Get Your Files Here !/09 - Behavioral Modeling/016 Example 8x1 Mux using 4x1 mux and 2x1 mux_en.vtt

2.6 kB

~Get Your Files Here !/09 - Behavioral Modeling/017 Example AND gate using 2x1 Mux.mp4

5.6 MB

~Get Your Files Here !/09 - Behavioral Modeling/017 Example AND gate using 2x1 Mux_en.vtt

2.1 kB

~Get Your Files Here !/09 - Behavioral Modeling/018 Example 1x8 Demux.mp4

3.4 MB

~Get Your Files Here !/09 - Behavioral Modeling/018 Example 1x8 Demux_en.vtt

704 B

~Get Your Files Here !/09 - Behavioral Modeling/019 Example Full Adder & 4-bit Full Adder.mp4

17 MB

~Get Your Files Here !/09 - Behavioral Modeling/019 Example Full Adder & 4-bit Full Adder_en.vtt

3.1 kB

~Get Your Files Here !/09 - Behavioral Modeling/020 Example 3x8 Decoder and 3x8 Decoder using 2x4 decoder.mp4

10 MB

~Get Your Files Here !/09 - Behavioral Modeling/020 Example 3x8 Decoder and 3x8 Decoder using 2x4 decoder_en.vtt

2.0 kB

~Get Your Files Here !/09 - Behavioral Modeling/021 Example 8x3 encoder.mp4

2.4 MB

~Get Your Files Here !/09 - Behavioral Modeling/021 Example 8x3 encoder_en.vtt

477 B

~Get Your Files Here !/09 - Behavioral Modeling/022 Example Priority encoder.mp4

7.8 MB

~Get Your Files Here !/09 - Behavioral Modeling/022 Example Priority encoder_en.vtt

1.4 kB

~Get Your Files Here !/09 - Behavioral Modeling/023 Example Seven Segment Display.mp4

13 MB

~Get Your Files Here !/09 - Behavioral Modeling/023 Example Seven Segment Display_en.vtt

1.9 kB

~Get Your Files Here !/09 - Behavioral Modeling/024 Example ALU.mp4

5.4 MB

~Get Your Files Here !/09 - Behavioral Modeling/024 Example ALU_en.vtt

863 B

~Get Your Files Here !/09 - Behavioral Modeling/025 Sequential Logic Circuits List of Examples.mp4

8.1 MB

~Get Your Files Here !/09 - Behavioral Modeling/025 Sequential Logic Circuits List of Examples_en.vtt

1.1 kB

~Get Your Files Here !/09 - Behavioral Modeling/026 Example D Flip Flop vs D-Latch.mp4

17 MB

~Get Your Files Here !/09 - Behavioral Modeling/026 Example D Flip Flop vs D-Latch_en.vtt

2.1 kB

~Get Your Files Here !/09 - Behavioral Modeling/027 Example Synchronous Reset D-Flip flop , Asynchronous Reset D-Flip flop.mp4

4.1 MB

~Get Your Files Here !/09 - Behavioral Modeling/027 Example Synchronous Reset D-Flip flop , Asynchronous Reset D-Flip flop_en.vtt

1.2 kB

~Get Your Files Here !/09 - Behavioral Modeling/028 Example T-Flip Flop.mp4

8.1 MB

~Get Your Files Here !/09 - Behavioral Modeling/028 Example T-Flip Flop_en.vtt

2.2 kB

~Get Your Files Here !/09 - Behavioral Modeling/029 Example Master-slave JK Flip Flop.mp4

6.1 MB

~Get Your Files Here !/09 - Behavioral Modeling/029 Example Master-slave JK Flip Flop_en.vtt

1.3 kB

~Get Your Files Here !/09 - Behavioral Modeling/030 Example Counter.mp4

19 MB

~Get Your Files Here !/09 - Behavioral Modeling/030 Example Counter_en.vtt

3.7 kB

~Get Your Files Here !/09 - Behavioral Modeling/031 Example UPDown Counter.mp4

27 MB

~Get Your Files Here !/09 - Behavioral Modeling/031 Example UPDown Counter_en.vtt

4.1 kB

~Get Your Files Here !/09 - Behavioral Modeling/032 Example clock divider using counter- Divide by 2,4,8,.mp4

14 MB

~Get Your Files Here !/09 - Behavioral Modeling/032 Example clock divider using counter- Divide by 2,4,8,_en.vtt

1.7 kB

~Get Your Files Here !/09 - Behavioral Modeling/033 Example Pulse Generator Mod-3 pulse generator.mp4

19 MB

~Get Your Files Here !/09 - Behavioral Modeling/033 Example Pulse Generator Mod-3 pulse generator_en.vtt

2.0 kB

~Get Your Files Here !/09 - Behavioral Modeling/034 Example Divide by 3 clock.mp4

18 MB

~Get Your Files Here !/09 - Behavioral Modeling/034 Example Divide by 3 clock_en.vtt

2.4 kB

~Get Your Files Here !/09 - Behavioral Modeling/035 Example Ring Counter vs Jonson Counter.mp4

12 MB

~Get Your Files Here !/09 - Behavioral Modeling/035 Example Ring Counter vs Jonson Counter_en.vtt

1.9 kB

~Get Your Files Here !/09 - Behavioral Modeling/036 Example Shift Registers SISO, SIPO, PISO,PIPO.mp4

13 MB

~Get Your Files Here !/09 - Behavioral Modeling/036 Example Shift Registers SISO, SIPO, PISO,PIPO_en.vtt

1.7 kB

~Get Your Files Here !/09 - Behavioral Modeling/037 Example LFSR (Linear Feedback Shift Register).mp4

35 MB

~Get Your Files Here !/09 - Behavioral Modeling/037 Example LFSR (Linear Feedback Shift Register)_en.vtt

5.1 kB

~Get Your Files Here !/09 - Behavioral Modeling/038 memory design.mp4

27 MB

~Get Your Files Here !/09 - Behavioral Modeling/038 memory design_en.vtt

3.8 kB

~Get Your Files Here !/10 - Switch level modeling/001 Switch level modeling.mp4

18 MB

~Get Your Files Here !/10 - Switch level modeling/001 Switch level modeling_en.vtt

3.2 kB

~Get Your Files Here !/11 - Test bench/001 Functional simulation.mp4

27 MB

~Get Your Files Here !/11 - Test bench/001 Functional simulation_en.vtt

4.6 kB

~Get Your Files Here !/11 - Test bench/002 Example - Test bench for counter design.mp4

62 MB

~Get Your Files Here !/11 - Test bench/002 Example - Test bench for counter design_en.vtt

5.4 kB

~Get Your Files Here !/11 - Test bench/003 Example - Test bench for Pulse generator.mp4

58 MB

~Get Your Files Here !/11 - Test bench/003 Example - Test bench for Pulse generator_en.vtt

5.6 kB

~Get Your Files Here !/11 - Test bench/external-assets-links.txt

412 B

~Get Your Files Here !/12 - Functions & Task and system tasks/001 Functions & tasks and system tasks.mp4

50 MB

~Get Your Files Here !/12 - Functions & Task and system tasks/001 Functions & tasks and system tasks_en.vtt

5.6 kB

~Get Your Files Here !/12 - Functions & Task and system tasks/002 File based system tasks and random generator system task.mp4

68 MB

~Get Your Files Here !/12 - Functions & Task and system tasks/002 File based system tasks and random generator system task_en.vtt

7.4 kB

~Get Your Files Here !/12 - Functions & Task and system tasks/003 Read file and write in to memory system task.mp4

19 MB

~Get Your Files Here !/12 - Functions & Task and system tasks/003 Read file and write in to memory system task_en.vtt

2.0 kB

~Get Your Files Here !/12 - Functions & Task and system tasks/004 Programming Language Interface.mp4

14 MB

~Get Your Files Here !/12 - Functions & Task and system tasks/004 Programming Language Interface_en.vtt

1.3 kB

~Get Your Files Here !/12 - Functions & Task and system tasks/external-assets-links.txt

633 B

~Get Your Files Here !/13 - FSM/001 FSM ( Finite State Machine) & Hardware modeling of FSM, Example Verilog code.mp4

126 MB

~Get Your Files Here !/13 - FSM/001 FSM ( Finite State Machine) & Hardware modeling of FSM, Example Verilog code_en.vtt

23 kB

~Get Your Files Here !/13 - FSM/002 Example FSM - Divide by 2 clock.mp4

12 MB

~Get Your Files Here !/13 - FSM/002 Example FSM - Divide by 2 clock_en.vtt

1.9 kB

~Get Your Files Here !/13 - FSM/003 Example FSM- Divide by 3 clock.mp4

22 MB

~Get Your Files Here !/13 - FSM/003 Example FSM- Divide by 3 clock_en.vtt

2.6 kB

~Get Your Files Here !/14 - Sequence detector using FSM with complete Design & TB/001 Sequence detector using FSM with complete Design & TB.mp4

65 MB

~Get Your Files Here !/14 - Sequence detector using FSM with complete Design & TB/001 Sequence detector using FSM with complete Design & TB_en.vtt

8.9 kB

~Get Your Files Here !/14 - Sequence detector using FSM with complete Design & TB/002 Sequence detector using FSM output waveform.mp4

13 MB

~Get Your Files Here !/14 - Sequence detector using FSM with complete Design & TB/002 Sequence detector using FSM output waveform_en.vtt

1.2 kB

~Get Your Files Here !/14 - Sequence detector using FSM with complete Design & TB/external-assets-links.txt

212 B

~Get Your Files Here !/15 - Project 1 Memory controller/001 Memory controller with Design & TB.mp4

93 MB

~Get Your Files Here !/15 - Project 1 Memory controller/001 Memory controller with Design & TB_en.vtt

10 kB

~Get Your Files Here !/15 - Project 1 Memory controller/external-assets-links.txt

212 B

~Get Your Files Here !/16 - Project 2 FIFO/001 FIFO Lecture.mp4

1.1 MB

~Get Your Files Here !/16 - Project 2 FIFO/001 FIFO Lecture_en.vtt

60 B

~Get Your Files Here !/16 - Project 2 FIFO/002 Introduction to FIFO.mp4

32 MB

~Get Your Files Here !/16 - Project 2 FIFO/002 Introduction to FIFO_en.vtt

4.4 kB

~Get Your Files Here !/16 - Project 2 FIFO/003 Write Read Operation of Normal RAM.mp4

27 MB

~Get Your Files Here !/16 - Project 2 FIFO/003 Write Read Operation of Normal RAM_en.vtt

3.8 kB

~Get Your Files Here !/16 - Project 2 FIFO/004 FIFO IO (input & Outputs).mp4

8.0 MB

~Get Your Files Here !/16 - Project 2 FIFO/004 FIFO IO (input & Outputs)_en.vtt

1.4 kB

~Get Your Files Here !/16 - Project 2 FIFO/005 Block Diagram and Architecture of FIFO.mp4

44 MB

~Get Your Files Here !/16 - Project 2 FIFO/005 Block Diagram and Architecture of FIFO_en.vtt

4.2 kB

~Get Your Files Here !/16 - Project 2 FIFO/006 Connection of FIFO design & Test bench environment.mp4

19 MB

~Get Your Files Here !/16 - Project 2 FIFO/006 Connection of FIFO design & Test bench environment_en.vtt

3.1 kB

~Get Your Files Here !/16 - Project 2 FIFO/007 Verilog HDL for FIFO design.mp4

89 MB

~Get Your Files Here !/16 - Project 2 FIFO/007 Verilog HDL for FIFO design_en.vtt

12 kB

~Get Your Files Here !/16 - Project 2 FIFO/008 Verilog HDL code for FIFO Test Bench.mp4

148 MB

~Get Your Files Here !/16 - Project 2 FIFO/008 Verilog HDL code for FIFO Test Bench_en.vtt

15 kB

~Get Your Files Here !/16 - Project 2 FIFO/009 Run the simulation and finding errors and Analyze the waveform Results.mp4

61 MB

~Get Your Files Here !/16 - Project 2 FIFO/009 Run the simulation and finding errors and Analyze the waveform Results_en.vtt

6.8 kB

~Get Your Files Here !/16 - Project 2 FIFO/external-assets-links.txt

78 B

~Get Your Files Here !/17 - Project 3 Hamming code complete Design & TB for error detection & correction/001 Hamming code complete Design & TB for error detection & correction.mp4

214 MB

~Get Your Files Here !/17 - Project 3 Hamming code complete Design & TB for error detection & correction/001 Hamming code complete Design & TB for error detection & correction_en.vtt

20 kB

~Get Your Files Here !/17 - Project 3 Hamming code complete Design & TB for error detection & correction/external-assets-links.txt

689 B

~Get Your Files Here !/18 - FPGA/001 FPGA.mp4

132 MB

~Get Your Files Here !/18 - FPGA/001 FPGA_en.vtt

15 kB

~Get Your Files Here !/Bonus Resources.txt

386 B