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[ DevCourseWeb.com ] Udemy - Hands-on development of cpu- soc on FPGA using vhdl(verilog)
- Date: 2026-04-28
- Size: 2.5 GB
- Files: 22
File Name
Size
Get Bonus Downloads Here.url
182 B
~Get Your Files Here !/1 -Introduction.mp4
20 MB
~Get Your Files Here !/10 -How to design a simple ALU.mp4
47 MB
~Get Your Files Here !/11 -architecture of a register bank.mp4
69 MB
~Get Your Files Here !/12 -how to handle multiple function units. introducing memory buffers.mp4
52 MB
~Get Your Files Here !/13 -how to connect different units using the control.mp4
122 MB
~Get Your Files Here !/14 -how to control memory operation, register operation, alu operation etc.mp4
291 MB
~Get Your Files Here !/15 -how control handles cache misses and cache hit.mp4
122 MB
~Get Your Files Here !/16 -how to setup the cache control for hit, miss, cache address and memory address.mp4
144 MB
~Get Your Files Here !/17 -the cache control.mp4
163 MB
~Get Your Files Here !/18 -888.mp4
440 MB
~Get Your Files Here !/19 -top wiring and conclusion.mp4
106 MB
~Get Your Files Here !/2 -Architecture of the design.mp4
46 MB
~Get Your Files Here !/3 -accessing resource file.mp4
105 MB
~Get Your Files Here !/3 -class_resources.zip
11 MB
~Get Your Files Here !/4 -How to design the program memory.mp4
38 MB
~Get Your Files Here !/5 -how to link program memory to instruction buffer and program counter buffer.mp4
83 MB
~Get Your Files Here !/6 -Extracting instruction set from RISC-V datasheet.mp4
250 MB
~Get Your Files Here !/7 -introducing the counter-track out-of-order execution.mp4
168 MB
~Get Your Files Here !/8 -how to setup the read and write register alias table.mp4
194 MB
~Get Your Files Here !/9 -feedback how to return registers after instruction exec using output buffers.mp4
97 MB
~Get Your Files Here !/Bonus Resources.txt
386 B