[ CourseMega.com ] Udemy - UART Design and Simulation using Verilog HDL programming

File Name

Size

Get Bonus Downloads Here.url

180 B

~Get Your Files Here !/01 - Introduction/001 Preview.mp4

27 MB

~Get Your Files Here !/01 - Introduction/001 Preview_en.vtt

4.5 kB

~Get Your Files Here !/01 - Introduction/002 Introduction to Serial Communication.mp4

6.2 MB

~Get Your Files Here !/01 - Introduction/002 Introduction to Serial Communication_en.vtt

1.1 kB

~Get Your Files Here !/01 - Introduction/003 Limitations of parallel communication and Advantage of Serial communication.mp4

24 MB

~Get Your Files Here !/01 - Introduction/003 Limitations of parallel communication and Advantage of Serial communication_en.vtt

2.8 kB

~Get Your Files Here !/01 - Introduction/004 Synchronous & Asynchronous Serial communication.mp4

5.8 MB

~Get Your Files Here !/01 - Introduction/004 Synchronous & Asynchronous Serial communication_en.vtt

970 B

~Get Your Files Here !/02 - Introduction to UART/001 What is UART.mp4

6.9 MB

~Get Your Files Here !/02 - Introduction to UART/001 What is UART_en.vtt

1.4 kB

~Get Your Files Here !/02 - Introduction to UART/002 Data format of UART.mp4

3.3 MB

~Get Your Files Here !/02 - Introduction to UART/002 Data format of UART_en.vtt

632 B

~Get Your Files Here !/02 - Introduction to UART/003 Transmission & Reception operations in UART.mp4

30 MB

~Get Your Files Here !/02 - Introduction to UART/003 Transmission & Reception operations in UART_en.vtt

4.8 kB

~Get Your Files Here !/02 - Introduction to UART/004 Block diagram for UART.mp4

10 MB

~Get Your Files Here !/02 - Introduction to UART/004 Block diagram for UART_en.vtt

2.8 kB

~Get Your Files Here !/03 - Implementation of UART modules/001 Baud rate generator.mp4

12 MB

~Get Your Files Here !/03 - Implementation of UART modules/001 Baud rate generator_en.vtt

2.1 kB

~Get Your Files Here !/03 - Implementation of UART modules/002 Verilog HDL for Baud rate generator.mp4

93 MB

~Get Your Files Here !/03 - Implementation of UART modules/002 Verilog HDL for Baud rate generator_en.vtt

10 kB

~Get Your Files Here !/03 - Implementation of UART modules/003 FSM for UART Transmitter.mp4

6.7 MB

~Get Your Files Here !/03 - Implementation of UART modules/003 FSM for UART Transmitter_en.vtt

1.4 kB

~Get Your Files Here !/03 - Implementation of UART modules/004 FSM for UART Receiver.mp4

5.5 MB

~Get Your Files Here !/03 - Implementation of UART modules/004 FSM for UART Receiver_en.vtt

1.2 kB

~Get Your Files Here !/03 - Implementation of UART modules/005 Test bench environment.mp4

22 MB

~Get Your Files Here !/03 - Implementation of UART modules/005 Test bench environment_en.vtt

3.5 kB

~Get Your Files Here !/03 - Implementation of UART modules/006 Hands on Verilog HDL for UART Transmitter with its Test Bench.mp4

531 MB

~Get Your Files Here !/03 - Implementation of UART modules/006 Hands on Verilog HDL for UART Transmitter with its Test Bench_en.vtt

46 kB

~Get Your Files Here !/03 - Implementation of UART modules/007 Hands on Verilog HDL for UART Receiver with its Test Bench.mp4

326 MB

~Get Your Files Here !/03 - Implementation of UART modules/007 Hands on Verilog HDL for UART Receiver with its Test Bench_en.vtt

28 kB

~Get Your Files Here !/03 - Implementation of UART modules/008 Hands on Added Logic for sample ticks in Verilog HDL for UART Receiver with TB.mp4

251 MB

~Get Your Files Here !/03 - Implementation of UART modules/008 Hands on Added Logic for sample ticks in Verilog HDL for UART Receiver with TB_en.vtt

26 kB

~Get Your Files Here !/Bonus Resources.txt

386 B